We have a very exciting opportunity for a Senior / Lead Verification Engineer in Cambridge.
Our client is expanding their DV team at a key growth stage, offering a rare opportunity to join early and genuinely shape verification methodology, standards, and technical direction as the team scales.
The work is focused on production-grade open-source silicon, including the Ibex RISC-V CPU and OpenTitan security platform, developed in collaboration with world-leading partners such as Google. This is real silicon used as a foundation for secure and scalable compute systems.
You’ll be working on industrial-strength verification across block and system-level designs, including RISC-V cores, cryptographic IP, and critical SoC peripherals, with strong emphasis on quality, security, and robustness.
What you’ll be doing
- Designing, building, and debugging SystemVerilog/UVM verification environments
- Writing verification plans, test cases, and coverage models
- Reviewing and debugging open-source CPU/security IP and regression issues
- Supporting and improving test infrastructure and CI flows
- Collaborating closely with global partners to support successful silicon tapeouts
What they’re looking for
Essential:
- 5+ years’ experience in design verification (CPU and/or GPU ideally)
- Strong hands-on experience with SystemVerilog and UVM
- Full lifecycle experience through to tapeout / sign-off
- Strong coding skills in C and/or Python for automation
- Experience working in Git/GitHub collaborative environments
Desirable:
- Exposure to formal verification (e.g. JasperGold)
- Experience with RISC-V or ISA-level verification
- Interest in security / cryptographic verification
- Experience with silicon bring-up or post-silicon debug
- Technical leadership or mentoring experience
If interested please get in touch and send your CV to tee@microtech-global.com
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