Senior FPGA Engineer

London (Hybrid: 4 days onsite)

Industry leading compensation

Quant Capital is partnering with a global trading firm building a greenfield FPGA team focused on ultra-low latency, high-throughput hardware acceleration. This is a small, senior engineering group delivering compute infrastructure integrated directly into trading, research, and networking pipelines, with strong emphasis on clean engineering, tooling, and end-to-end ownership.

What you’ll be doing

• Design and implement latency-optimised FPGA systems (Verilog/SystemVerilog)
• Build high-speed modules (e.g., PCIe, Ethernet, DDR/QDR) with deep pipelining and careful datapath design
• Validate designs using simulation and verification tooling (e.g., Verilator, Cocotb; formal where appropriate)
• Work cross-functionally with software, infra/networking, and research to co-design tightly coupled platforms
• Contribute to developer productivity: tooling, flows, reusable components, and better ways of building/testing hardware

What we’re looking for

• Strong RTL/FPGA fundamentals and experience delivering complex, optimised designs
• Solid grasp of timing closure, latency budgeting, and hardware-level performance tuning
• Experience with toolchains (Vivado, Quartus) and practical debugging workflows
• Programming ability in a high-level language (C/C++/Python or similar) to support test/automation/tooling
• Comfortable owning the full development cycle: design → test → deploy → iterate in production environments
• High-performance networking acceleration (SERDES, PCIe integration, ethernet/infiniband style problems)
• Build from scratch with real architectural influence in a small, high-calibre team
• Full-lifecycle ownership with minimal overhead and real impact on live systems
• Strong engineering culture that values tools, reliability, and iteration speed

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