Senior Principal Design Engineer – Chiplet & IP Leadership

Cadence in Edinburgh is seeking a Sr Principal Design Engineer to lead complex Silicon programs and integrate cutting-edge IP solutions. The role involves collaborating with global teams to develop innovative Chiplet solutions for high-tech markets.

Ideal candidates will have over 12 years of experience in the microelectronics industry, a degree in Electronic Engineering, and strong skills in Verilog RTL design and team leadership. Join us to make an impact in technology.

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