CPU Research Engineer (Contractor)

Key Responsibilities

1. Research and develop novel out-of-order execution techniques to improve IPC and energy efficiency of mobile CPUs.
2. Analyse and optimise front-end pipeline stages including branch prediction, fetch, and decode.
3. Investigate bottlenecks in the out-of-order backend: issue queues, register renaming, reorder buffer, and execution units.
4. Develop and maintain cycle‑accurate micro‑architectural simulation models (e.g. gem5) to evaluate OOO design trade‑offs.
5. Propose micro‑architectural enhancements targeting performance‑per‑watt optimisation for mobile workloads.
6. Conduct workload characterisation and micro‑architectural profiling using hardware performance counters and simulation.
7. Evaluate and integrate state‑of‑the‑art academic research into practical CPU design proposals.

Required

1. Master/PhD degree in Computer Science/Engineering/Physics etc.
2. Strong knowledge of advanced computer architectures, superscalar processor design, and compiler design principles.
3. Deep understanding of speculative execution, branch prediction, and out-of-order execution.
4. Strong programming skills in C, C++, Python, assembly languages (Arm64 assembly or RISC‑V assembly), and scripting languages.
5. Experience with cycle‑accurate microarchitecture simulation and performance modelling.
6. Understanding of instruction scheduling, register allocation, and code generation.
7. Highly‑motivated and independent individual with a strong desire for knowledge acquisition.

Desired

1. Strong knowledge of advanced branch predictors and prefetching mechanisms.
2. Experience with gem5, Sniper, ChampSim, or other cycle‑accurate detailed microarchitecture simulators.
3. Experience with LLVM backend development or custom ISA extension implementation.
4. Strong knowledge of profile‑guided optimisation (PGO) and feedback‑directed optimisation.
5. Experience with compiler development (LLVM, GCC) or compiler optimisation techniques.
6. Experience with OS kernel development and understanding of scheduler and memory manager internals.
7. Knowledge of binary translation, dynamic binary instrumentation, or JIT compilation techniques.
8. Understanding of hardware‑enforced security mechanisms (CFI, PAC, BTI, MTE on Arm).
9. Experience with co‑simulation frameworks integrating ISA simulators with compiler toolchains.
10. Familiarity with emerging technologies: processing‑in‑memory (PIM), near‑data processing, chiplet architectures.
11. Familiarity with domain‑specific architectures and accelerator‑compiler co‑design methodologies.

This job description is only an outline of the tasks, responsibilities and outcomes required of the role. The jobholder will carry out any other duties as may be reasonably required by his/her line manager. The job description and personal specification may be reviewed on an ongoing basis in accordance with the changing needs of Huawei Research and Development UK Limited.

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