Qualcomm is seeking talented Graduate Server CPU Physical Design Engineers to join the Nuvia Data Centre CPU team in Cambridge, UK. The team is developing next‑generation, high‑performance, power‑efficient custom CPU cores for advanced compute and server‑class platforms that will help transform the industry.
About the role
This is an exciting opportunity for graduates who want to start their engineering career working on cutting‑edge CPU technology. You will learn from experienced engineers and contribute to the physical implementation of high‑performance CPU designs, gaining exposure to the full journey from RTL/netlist through implementation, timing closure, signoff, and silicon delivery.
You will work with global teams across CPU architecture, RTL design, circuit design, CAD, SoC integration, timing, power, and post‑silicon validation. Over time, you will develop the skills needed to contribute to demanding performance, power, and area (PPA) targets for advanced server‑class CPU products.
Key Responsibilities
- Learn and contribute to CPU block physical implementation from RTL/netlist to GDS, including synthesis, floorplanning, placement, clock tree synthesis, routing, optimization, ECOs, and signoff.
- Support timing closure and implementation convergence across multiple modes, corners, and operating conditions.
- Work with experienced engineers to analyse and improve performance, power, and area for high‑performance, low‑power CPU designs.
- Help debug physical design issues related to timing, congestion, routing, clocking, power, physical verification, DRC/LVS, and ECO closure.
- Use industry‑standard EDA tools and flows for synthesis, place and route, static timing analysis, power analysis, and physical verification.
- Develop scripting and automation skills to improve productivity, data analysis, and design‑flow efficiency.
- Collaborate with RTL, architecture, CAD, circuits, SoC, and post‑silicon teams to understand design intent and implementation trade‑offs.
- Learn how CPU designs progress from early concept through implementation, verification, signoff, and productization.
- Contribute to methodology improvements, automation, documentation, and data‑driven analysis under the guidance of senior engineers.
Required Skills and Experience
- Good understanding of digital logic design, CMOS fundamentals, VLSI design, or semiconductor design concepts.
- Basic understanding of static timing analysis concepts, including setup, hold, clocking, timing paths, and timing constraints.
- Exposure to scripting or programming using one or more of: TCL, Python, Perl.
- Strong analytical and problem‑solving skills.
- Ability to learn complex technical concepts quickly and apply them in a practical engineering environment.
- Good communication skills and willingness to work in a collaborative, global engineering team.
Preferred Qualifications
- University coursework, internship, thesis, or project work in VLSI, ASIC design, physical design, digital IC design, computer architecture, or EDA.
- Familiarity with EDA tools used for synthesis, place and route, STA, power analysis, or physical verification.
- Experience with Verilog/SystemVerilog, digital logic design, or RTL concepts.
- Understanding of CPU architecture, pipelines, caches, clocking, or low‑power design concepts.
- Experience using Linux‑based engineering environments.
- Data analysis skills and ability to work with reports, logs, metrics, and design results.
- Curiosity about how high‑performance CPU designs are physically implemented and optimised.
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related technical field.
- Or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Microelectronics, Semiconductor Engineering, or a related technical field.
- Or PhD in a relevant technical field with research or project experience related to digital design, VLSI, ASIC implementation, CPU design, or semiconductor design.
- Recent graduates and candidates with internship, industrial placement, academic research, or project experience in relevant areas are encouraged to apply.
What You Will Learn
- Server CPU physical design and implementation methodology.
- RTL/netlist to GDS implementation flows.
- Synthesis, floorplanning, placement, CTS, routing, ECOs, and signoff.
- Static timing analysis and timing closure.
- Power, area, congestion, and routability trade‑offs.
- Physical verification and design quality checks.
- Advanced‑node implementation challenges.
- Automation and scripting for design‑flow productivity.
- Cross‑functional collaboration across CPU design, CAD, circuits, SoC, and post‑silicon teams.
What We Value
- Strong engineering fundamentals and a passion for semiconductor design.
- Enjoy solving complex technical problems.
- Curiosity about CPU design, physical implementation, and advanced compute platforms.
- Ability to learn quickly and take ownership of technical tasks.
- Structured, analytical approach to debugging and problem‑solving.
- Clear communication and effective collaboration with others.
- Motivation to build high‑performance, power‑efficient server CPU products.
- Initiative, curiosity, attention to detail, and a continuous‑improvement mindset.
Benefits and Perks
- Competitive compensation package, including base salary, performance‑related bonus, and equity opportunities.
- Employee Stock Purchase Plan and equity programs supporting share ownership and long‑term participation.
- Pension and retirement support, including a matching pension scheme.
- Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.
- Maternity, paternity, family, and extended leave support.
- Education assistance and tuition support to enable continued learning and professional development.
- Relocation and immigration support where applicable.
- Employee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.
- Opportunities to connect through employee networks, community programs, volunteering, and social groups.
- Subsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.
- Flexible, collaborative, and technically challenging work environment where you can learn from highly skilled engineers working on advanced CPU technology.
Why Join the Nuvia Data Center CPU Team in Cambridge?
Cambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post‑silicon validation. Target products include high‑performance CPUs and GPUs, ultra‑low‑power IoT devices, and wearables such as smart glasses, smart watches, and earbuds. The Nuvia Data Centre CPU team offers graduates the opportunity to begin their careers working on advanced custom CPU technology for next‑generation compute platforms. You will join a world‑class engineering team working on demanding server‑class CPU implementation challenges in advanced technology nodes. You will receive mentorship from experienced engineers while building deep expertise in CPU physical design, timing, power, and implementation methodology.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑accommodations@qualcomm.com or call Qualcomm’s toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
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