Formal Verification Engineer Axiomise

The Formal Verification Engineer independently executes formal verification activities for complex hardware designs, ensuring functional correctness, robustness, and quality before tape-out. The role involves developing and optimizing properties, running advanced formal verification techniques, mentoring junior engineers, and collaborating closely with design teams to achieve verification closure.

Responsibilities

• Contribute to equivalence checking, verification planning, and coverage closure activities
• Debug counterexamples and collaborate with design and verification teams to resolve issues
• Develop and maintain formal verification environments, writing assertions to validate RTL designs against specifications
• Support improvements to verification flows, automation, and documentation while building expertise in formal methodologies
• Run formal analysis to identify bugs and corner-case issues, with guidance on complex scenarios

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