Job Description
Senior FPGA Engineer | UK (Hybrid)
My client is an innovative technology company developing advanced networking solutions for high-performance computing environments. Their work focuses on improving system performance and efficiency at scale.
They’re looking for an experienced FPGA Engineer to develop high-speed interfaces between compute platforms and next-generation networking systems, taking designs from prototype through to production.
Responsibilities
- Define microarchitecture with cross-functional teams
- RTL design, synthesis, and timing closure
- Verification planning and simulation (SystemVerilog)
- Develop and validate FPGA lab platforms
Requirements
- Strong FPGA design experience in high-speed networking (100Gbps+)
- Experience with PCIe, RDMA, CXL, NVLink or similar
- Proficient in SystemVerilog, Verilog, VHDL
- Experience with FPGA tools (Vivado, Quartus, Vitis)
- Scripting skills (TCL, Python)
- Embedded systems and host interface experience
Bonus Skills
- Experience with advanced FPGA platforms (Versal, Agilex)
- Exposure to HPC or data centre systems
If this sounds like you, please apply below
#J-18808-Ljbffr”, “datePosted”: “2026-05-17”, “hiringOrganization”: { “@type”: “Organization”, “name”: “Energy Jobline ZR”, “sameAs”: “https://uk.whatjobs.com/pub_api__cpl__435475614__4861?utm_campaign=publisher&utm_medium=api&utm_source=4861&geoID=11133” }, “jobLocation”: { “@type”: “Place”, “address”: { “@type”: “PostalAddress”, “addressLocality”: “Farringdon” } } }Job Description
Senior FPGA Engineer | UK (Hybrid)
My client is an innovative technology company developing advanced networking solutions for high-performance computing environments. Their work focuses on improving system performance and efficiency at scale.
They’re looking for an experienced FPGA Engineer to develop high-speed interfaces between compute platforms and next-generation networking systems, taking designs from prototype through to production.
Responsibilities
- Define microarchitecture with cross-functional teams
- RTL design, synthesis, and timing closure
- Verification planning and simulation (SystemVerilog)
- Develop and validate FPGA lab platforms
Requirements
- Strong FPGA design experience in high-speed networking (100Gbps+)
- Experience with PCIe, RDMA, CXL, NVLink or similar
- Proficient in SystemVerilog, Verilog, VHDL
- Experience with FPGA tools (Vivado, Quartus, Vitis)
- Scripting skills (TCL, Python)
- Embedded systems and host interface experience
Bonus Skills
- Experience with advanced FPGA platforms (Versal, Agilex)
- Exposure to HPC or data centre systems
If this sounds like you, please apply below
#J-18808-Ljbffr…
