A world-renowned semiconductor giant is seeking a Staff Engineer to join their ASICS Engineering group in Cambridge. This role is a key contributor to the design, implementation, and verification of complex power‑management blocks and subsystems for a market‑leading range of connectivity, Voice, and Music chips.
Role
In this position, the successful candidate will define architectures for complex PMIC blocks, execute development plans, and ensure the delivery of fully verified subsystems. This involves solving complex problems in a tightly constrained environment and staying at the forefront of analogue design developments to enhance macro‑level architectures and chip features.
Key Responsibilities
- Define and execute the architecture and development of complex Power‑management blocks (SMPS, LDOs).
- Lead the verification of analogue sub‑cells and power‑management subsystems.
- Collaborate with macro leads to ensure high‑quality, timely delivery of solutions.
- Provide technical expertise and documentation for block characterisation across departments.
Requirements
- Experience: Typically 5+ years of experience in analogue design, specifically with Power Management IPs such as SMPS and LDOs.
- Technical Skills: Fully competent in Cadence and Mentor analogue design/verification tools. Knowledge of Matlab for architectural specification is a plus.
- Education: A degree in Electronics, Maths, Science, or a related Engineering field.
- Minimum Qualifications: Bachelor’s + 4 years, Master’s + 3 years, or PhD + 2 years of relevant ASIC experience.
- Soft Skills: Strong communication skills and a collaborative, team‑oriented mindset.
Location
This role is based at the Cambridge office, requiring a presence on‑site 5 days per week.
Interested?
Apply directly through LinkedIn, or send your CV to george@eu-recruit.com.
By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/).
#J-18808-Ljbffr”, “datePosted”: “2026-05-17”, “hiringOrganization”: { “@type”: “Organization”, “name”: “European Tech Recruit”, “sameAs”: “https://uk.whatjobs.com/pub_api__cpl__435467588__4861?utm_campaign=publisher&utm_medium=api&utm_source=4861&geoID=126” }, “jobLocation”: { “@type”: “Place”, “address”: { “@type”: “PostalAddress”, “addressLocality”: “Cambridge” } } }A world-renowned semiconductor giant is seeking a Staff Engineer to join their ASICS Engineering group in Cambridge. This role is a key contributor to the design, implementation, and verification of complex power‑management blocks and subsystems for a market‑leading range of connectivity, Voice, and Music chips.
Role
In this position, the successful candidate will define architectures for complex PMIC blocks, execute development plans, and ensure the delivery of fully verified subsystems. This involves solving complex problems in a tightly constrained environment and staying at the forefront of analogue design developments to enhance macro‑level architectures and chip features.
Key Responsibilities
- Define and execute the architecture and development of complex Power‑management blocks (SMPS, LDOs).
- Lead the verification of analogue sub‑cells and power‑management subsystems.
- Collaborate with macro leads to ensure high‑quality, timely delivery of solutions.
- Provide technical expertise and documentation for block characterisation across departments.
Requirements
- Experience: Typically 5+ years of experience in analogue design, specifically with Power Management IPs such as SMPS and LDOs.
- Technical Skills: Fully competent in Cadence and Mentor analogue design/verification tools. Knowledge of Matlab for architectural specification is a plus.
- Education: A degree in Electronics, Maths, Science, or a related Engineering field.
- Minimum Qualifications: Bachelor’s + 4 years, Master’s + 3 years, or PhD + 2 years of relevant ASIC experience.
- Soft Skills: Strong communication skills and a collaborative, team‑oriented mindset.
Location
This role is based at the Cambridge office, requiring a presence on‑site 5 days per week.
Interested?
Apply directly through LinkedIn, or send your CV to george@eu-recruit.com.
By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/).
#J-18808-Ljbffr…