Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

Job Responsibilities:

• Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
• Develop and execute verification plans, including testbench development using UVM methodology.
• Perform functional verification, debugging, and coverage analysis to ensure design correctness.
• Participate in SoC integration, testability (DFT) design, and overall front-end development flow.
• Collaborate with architecture, physical design, and software teams to ensure seamless integration.
• Contribute to automation and tooling improvements using scripting languages.

Job Requirements:

• Bachelor’s degree or above in Electrical Engineering, Computer Engineering, or related fields.
• Understanding of digital design fundamentals and IC development flow.
• Familiarity with Verilog/SystemVerilog and basic RTL design concepts.
• Exposure to verification methodologies (e.g., UVM) is a plus.
• Basic scripting skills (Python / Shell) preferred.
• Strong analytical thinking, problem-solving ability, and learning agility.

What They Offer:

• Opportunity to work on advanced ASIC/SoC projects with real-world impact.
• Exposure to both design and verification in a full front-end flow.
• Clear career progression in chip design and verification domains.

EA Registration Number: R

Business Registration Number: W. Licence Number: 18S9037

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