Senior FPGA Engineer

This is an opportunity to join a global team developing ultra-low latency technology.

You will oversee all aspects of FPGA system design, driving advancements to ensure my client maintains its technological advantage by building the next generation of infrastructure.

Responsibilities:

• Architecting and implementing RTL designs on high‑end FPGAs (Xilinx / Intel).
• Performing simulation, synthesis, P&R, and timing analysis for ultra‑low‑latency systems.
• Leading the definition of micro‑architectures and verification environments.
• Driving technical excellence across the FPGA team through mentorship and code reviews.
• Collaborating with firmware, software and infrastructure teams to optimise full‑stack performance.

Requirements:

• 7+ years’ FPGA / RTL design experience in timing‑critical systems.
• Strong background in SystemVerilog, synthesis, timing closure and verification.
• Hands‑on with Vivado / Quartus or equivalent toolchains.
• Familiarity with AXI, PCIe, Ethernet or custom high‑speed interfaces.

Bonus Skills:

• Exposure to high‑performance computing, networking or real‑time data systems.
• Knowledge of C/C++ or Python for tooling, verification or firmware collaboration.
• Appreciation for hardware–software co‑design and system‑level optimisation.

Apply now to join a global leader in an extremely high growth market!

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