Senior RTL CPU Architect — Midcore Microarchitecture

SiFive, Inc. is looking for a CPU Microarchitecture/RTL design engineer to be part of a team designing innovative CPU cores based on open‑source RISC‑V architecture. The role involves architecture, design, and verification of RISC‑V CPU features, ensuring successful collaboration across teams.

Candidates should have a BS or MS in relevant fields, 5+ years of CPU RTL design experience, and proficiency in RTL design languages. The position requires attention to detail, strong teamwork skills, and a collaborative mindset.

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