Senior AMS DV Engineer – SystemVerilog/UVM

Apple is seeking a Design Verification Engineer for its new London team. This role involves defining verification environments, coding test scenarios, and close collaboration with engineering teams. The ideal candidate will have strong knowledge of System Verilog, UVM, and experience in verification methods. A Master’s degree or equivalent experience is preferred. This position offers a chance to work in a creative environment that encourages diversity and innovation.#J-18808-Ljbffr…