Senior Verification Engineer – SoC/Chiplet Interconnects

A semiconductor solutions provider in the UK is seeking a Design Verification Engineer to create test plans for configurable IPs and build testbenches using UVM/SystemVerilog. The ideal candidate will have over 8 years of hands-on experience in verification at various levels and strong proficiency in Verilog and SystemVerilog. This role offers compensation commensurate with experience, performance incentives, and equity opportunities. #J-18808-Ljbffr