FinFET AMS Layout Engineer — Analog & High‑Speed IP

A leading semiconductor company in the UK seeks an AMS Layout Engineer with expertise in analog and mixed-signal circuits. The ideal candidate will work closely with circuit designers to produce layouts for high-speed SerDes I/O, PLLs, and ESD structures. Essential qualifications include experience with analog IP blocks, a solid understanding of signal integrity, and deep sub-micron CMOS layout experience. Familiarity with Cadence Virtuoso is also required, along with strong communication skills and the ability to estimate layout schedules. #J-18808-Ljbffr