Senior Verification Engineer - UVM & SystemVerilog Expert

A leading technology verification company in the United Kingdom seeks a contractor for verification environments of RTL designs. The candidate should have extensive experience in using hardware verification languages like SystemVerilog or Specman, and must be familiar with UVM methodologies. Understanding end-to-end verification processes and familiarity with tools like Mentor Questasim is essential. Competitive compensation is offered. #J-18808-Ljbffr