Digital Design Verification Engineer (SystemVerilog/UVM)

A leading tech company in the United Kingdom is looking for Digital Design Verification Engineers to focus on design verification of integrated circuits. Candidates should have a Master’s degree in Electrical / Computer Engineering and at least 3 years of relevant experience, or a Bachelor’s with 5 years experience. Strong skills in System Verilog and UVM are essential. The role involves responsibility for test benches, automated simulations, and leading the design verification team. #J-18808-Ljbffr