Salary: Very Attractive Rate
Location: N/A
Digital Design Verification Engineers (x2)
Your tasks and responsibilities
- Responsible for design verification of integrated circuits, using both directed tests and constrained random regressions
- Primary focus is on digital design verification, but proficiency with mixed signal design verification and creation / validation of models are strong advantages
- Proficiency in System Verilog and UVM, including: writing checkers and assertions, customizing constraints, getting functional coverage collection using cover groups, etc.
- Technical and team leadership – both within the internal project DV team, but also directly supporting demanding customers.
- Creation of test benches and automated verification simulations
- Performing block level and top level design verification
- Generation of relevant documentation (DV Plan, DV execution plan, customer reviews, etc.)
Your education and experiences
- Master’s degree in Electrical / Computer Engineering with 3 years of experience in Design Verification, or a Bachelor’s degree with 5 years of experience including at least 3 years in team or technology leadership role
- System Verilog / UVM based DV experience
- Collaborative and respectful team player with mentoring skills, and passionate about the team’s success
- Excellent communication skills (both oral and written) are required, as customer level technical interface and design / team leadership is necessary sometimes under high pressure situations.
- Experience with relevant CAD tools
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