Digital Verification Engineer

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Overview

Digital Verification Engineer

Qualifications

• Experience with I2C, SPI and good understanding of ASIC design flow
• Familiarity with System Verilog and UVM implementation
• Experience of setting up UVM test bench from scratch and hands on experience on developing UVM Components
• Experience of setting up GLS verification environment
• Hands-on experience on Assertions and Functional Coverage
• Automation of verification flow with Python/Perl in an industrial setting
• Independent, self-motivated, team player and able to follow through
• Understanding of Analog behavioral model; experience added advantage
• Automotive experience and requirements management experience is highly desirable

Additional

Principal ASIC Verification Recruitment Specialist

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