Physical Design Engineer: 7nm Flow & Signoff

A leading technology firm in the United Kingdom is seeking Physical Design Engineers specializing in digital IC design flow, particularly in TSMC 7nm process. Candidates should have experience with block-level timing closure and physical verification. The role involves responsibilities in clock constraints, floorplanning, and implementation of design views. Interested candidates can reach out via email for further information. #J-18808-Ljbffr