Lead Mixed Signal Design Verification Engineer
Salary: Very Attractive Rate
Location: N/A
Lead Mixed Signal Verification Engineer
- Interact with analog design team and develop behavioral models of analog design blocks in System Verilog
- Integrate the SV behavioral models in top level verification environment; provide debug support for models as and when needed
- Do periodic DMS netlist generation
- Contribute to the DMS testplan --- add description of testcases for verifying A-D connectivity
- Develop checks in the form of System Verilog assertions
- Develop DMS testcases and debug them in case of test failures
- Develop AMS simulation environment
- Develop AMS testplan – capture what all testcases make sense for AMS simulations
- Run AMS testcases and review waveforms with analog design team
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