Chipright is looking for Physical Design Engineers who are experts in the full digital IC design flow and specifically in floorplanning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities, and physical verification.
The scope of work includes the physical implementation of blocks in TSMC 7nm process, with the following responsibilities:
- Create clock constraints and perform block-level clock tree synthesis
- Ownership of block-level timing closure activities
- Floorplanning of the blocks
- Complete place and route of the blocks
- Physical verification of the blocks
- Signoff STA of the blocks
- Creation of all necessary design views for integration into top-level
- Implementation of top-level signoff-driven ECOs
- Contribute to top-level design closure and signoff
- Perform and ensure clean signoff checks for timing, physical verification, multi-voltage, formal, and IRDROP for all agreed blocks
- Organize regular review of tasks in progress or completed
- Complete all documentation associated with the above tasks
Requirements:
- Experience of advanced process nodes (16nm and lower) is highly desired
- Experience of Cadence Innovus or IC Compiler II is highly desired
Please contact natalia.bisaga@chipright.com for more details.
Equal Employment Opportunity statement: Chipright is an equal opportunities employer and welcomes applications from all qualified candidates.
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