Senior CPU RTL Engineer (RISC‑V, Chisel)

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Company: SiFive, Inc.
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A technology company specializing in CPU design is seeking a Senior RTL Design Engineer in Cambridge. You will be responsible for architecting and implementing features in RISC-V CPU core generators. The ideal candidate has 3+ years of design experience and a strong background in hardware design with Verilog/System Verilog or VHDL. Excellent collaboration skills and attention to detail are essential, and experience with tools like Git, Jira, and Confluence is preferred.#J-18808-Ljbffr…

Posted: April 17th, 2026