The Role
As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry‑leading CPU cores based on the revolutionary open‑source RISC‑V architecture. You will work in a fast‑paced, dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Responsibilities
- Architect, design, and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements that enable automatic configuration, documentation, verification testbenches, and packaged software.
- Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Develop microarchitecture specifications and share knowledge through excellent documentation and a culture of collaborative design.
Requirements
- BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
- Strong software engineering skills, including object‑oriented, aspect‑oriented, and functional programming, templated metaprogramming, compiler infrastructures for domain‑specific languages, data modeling for compiler passes, and test‑driven development with adaptive unit tests.
- Attention to detail and a focus on high‑quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
Nice‑to‑haves
- Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware.
- Knowledge of RISC‑V architecture.
- Expertise in CPU processor design areas such as instruction fetch, instruction decode, register renaming and instruction scheduling, vector units, or load‑store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
- Experience with Git/GitHub, Jira, Confluence.
Additional Information
This position requires successful background and reference checks and satisfactory proof of your right to work in the United Kingdom. Any offer of employment is contingent on the Company verifying that you are authorized to access export‑controlled technology under applicable export control laws, or that the Company can obtain the necessary export licenses or approvals.
Equal Opportunity
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
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