Early Career CAD Tools Optimisation Engineer (Design Verification)

As a CAD engineer, you will assist with delivering high‑quality infrastructure for automating chip design processes. With the increasing scale of chip designs, you will optimize the performance of simulation tools to maximize efficiency and reduce resource requirements (compute time and space). Your responsibilities include developing and deploying new methodologies with vendor and internal teams, and supporting and debugging issues on large‑scale simulations.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering, or a related field.
• Experience with RTL simulation tools.
• Foundation on Linux and grid computing systems.
• Knowledge of scripting languages such as Python or Perl.
• Strong interpersonal and analytical skills.
• Ability to work well within a team and be productive under tight schedules.
• Familiarity with Cadence tool chain.
• Experience with SystemVerilog, Verilog, or VHDL.
• Curiosity about GPU, PMU, CPU, SOC architecture, and micro‑architecture.

EEO Statement

Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.

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