Senior Design Verification Engineer

A well-funded AI hardware startup is building a next-generation compute platform aimed at dramatically improving AI inference performance and efficiency.

The company is assembling a high-calibre verification team ahead of first silicon and is looking for Verification Engineers who want to work close to architecture, software, and bring-up.

This is an opportunity to join at a genuinely formative stage: verification infrastructure is still being built, architecture is evolving rapidly, and engineers are expected to contribute well beyond traditional DV boundaries.

What You’ll Work On

• Verification of complex ASIC / processor subsystems for cutting-edge AI hardware
• Building verification environments and infrastructure from the ground up
• Developing scalable testbenches using modern software tooling
• Writing Python/C++ models, tooling, and reference implementations
• Coverage planning, debugging, and verification strategy definition
• Collaborating directly with architects and design engineers to influence microarchitecture decisions
• Contributing to tooling, flows, automation, and overall verification productivity

This is not a “throw tests over the wall” environment. Verification engineers are deeply embedded in technical discussions and play an active role in shaping the product.

What They’re Looking For

Strong experience in:

• ASIC or processor verification
• Complex subsystem or core-level verification
• SystemVerilog and verification methodologies such as UVM or cocotb
• Strong Python skills and genuine software engineering capability, beyond simple scripts
• Debugging challenging design and integration issues

Nice to have:

• Experience building models, infrastructure, or verification tooling
• Engineers with experience operating in fast-moving environments

The team is particularly interested in engineers who want to evolve toward a more software-heavy verification style, rather than purely traditional UVM execution work.

Environment & Culture

What makes the opportunity compelling is the level of ownership and technical exposure:

• Greenfield verification infrastructure
• Close interaction with architecture teams
• Real influence on methodology and tooling direction
• Opportunity to contribute beyond standard DV boundaries

The engineering group includes highly experienced silicon and systems engineers, with a collaborative and informal culture.

This role is likely to suit engineers who enjoy ownership and fast technical iteration. It is probably less suited to candidates looking for narrowly defined DV execution work.