Summary
As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU, ensuring Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions.
Description
This role requires a mix of strategic engineering along with hands‑on technical work, being responsible for implementing complete chip design from netlist to tapeout, and having hands‑on experience in physical design and large chip integration.
Responsibilities
- Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
- Contribute to innovation with the physical design team, develop methodologies and best known methods to enable outstanding GPU design.
- Develop PD guidelines and checklists and drive execution; be the focal point for place and route integration at the top level; plan short and long‑term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
- Apply creative problem‑solving under pressure to find new solutions.
Minimum Qualifications
- MSEE or equivalent is required.
- Deep experience with all aspects of ASIC integration including floorplanning, clock & power distribution, global signal planning, I/O planning, and hard IP integration.
Preferred Qualifications
- Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Familiarity with hierarchical design approach, top‑down design, budgeting, timing and physical convergence.
- Expertise in integrating IP from both internal and external vendors and ability to specify and drive IP requirements in the physical domain.
- Experience with large subsystem designs (>20M gates) at frequencies above 1 GHz applying new technologies.
- Experience with various process‑related design issues including design for yield and manufacturability, multi‑Vt strategies and thermal management.
- From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows.
Legal and Accessibility Commitments
At Apple, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.
At Apple, we believe accessibility is a fundamental human right, reflected in our culture, benefits and digital tools. By welcoming many perspectives, we help you build a career where you feel like you belong.
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As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU, ensuring Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions.
Description
This role requires a mix of strategic engineering along with hands‑on technical work, being responsible for implementing complete chip design from netlist to tapeout, and having hands‑on experience in physical design and large chip integration.
Responsibilities
- Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
- Contribute to innovation with the physical design team, develop methodologies and best known methods to enable outstanding GPU design.
- Develop PD guidelines and checklists and drive execution; be the focal point for place and route integration at the top level; plan short and long‑term work and goals with awareness of dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
- Apply creative problem‑solving under pressure to find new solutions.
Minimum Qualifications
- MSEE or equivalent is required.
- Deep experience with all aspects of ASIC integration including floorplanning, clock & power distribution, global signal planning, I/O planning, and hard IP integration.
Preferred Qualifications
- Knowledge of issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Familiarity with hierarchical design approach, top‑down design, budgeting, timing and physical convergence.
- Expertise in integrating IP from both internal and external vendors and ability to specify and drive IP requirements in the physical domain.
- Experience with large subsystem designs (>20M gates) at frequencies above 1 GHz applying new technologies.
- Experience with various process‑related design issues including design for yield and manufacturability, multi‑Vt strategies and thermal management.
- From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows.
Legal and Accessibility Commitments
At Apple, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.
At Apple, we believe accessibility is a fundamental human right, reflected in our culture, benefits and digital tools. By welcoming many perspectives, we help you build a career where you feel like you belong.
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