Ultra-Low Latency ASIC Engineer (FPGA/ASIC)

Jane Street is seeking an experienced ASIC Engineer in Greater London to design, test, and deploy advanced hardware designs. You’ll collaborate with teams in trading, networking, and research infrastructure while contributing to both FPGA and ASIC technologies.

Ideal candidates have over 4 years of experience in RTL design and verification, and expertise in ASIC design using Synopsys or Cadence. You should also be eager to utilize software engineering techniques to enhance the hardware design process.

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