Staff Verification Engineer — FPGA Systems & UVM Lead

Riverlane in Cambridge is looking for a Staff Verification Engineer to take ownership of verification across designs. This full-time, hybrid role offers a salary of £90,000 to £115,000, depending on experience, along with a comprehensive benefits package and bonus.

Successful candidates will have expertise in SystemVerilog and UVM, with experience in FPGA design verification. The opportunity is ideal for a proactive individual passionate about technology and innovation.

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