Senior Verification Engineer (f/m/div)

#WeAreIn for jobs that impact everyone’s life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Verification Engineer on our Research & Development team, you’ll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Your Role

Key responsibilities in your new role:

• Assist in developing and maintaining System Verilog – UVM test benches in collaboration with senior engineers and the team
• Contribute to creating and enhancing SV UVM verification components, with guidance and supervision from experienced team members
• Support debugging failing test cases to identify root causes, gaining experience with debugging tools and best practices
• Assist with defining functional coverage models and ensuring coverage goals are achieved under guidance
• Participate in team reviews, design discussions, and process improvements, contributing your ideas and learning from team members
• Help ensure test bench quality and sign-off targets are met, including coverage metrics and functional safety requirements

Your Profile

Qualifications and skills to help you succeed:

• A Bachelor’s degree in Electrical/Electronic Engineering or a related field
• At least 1–2 years of experience in Verification Engineering, with hands‑on exposure to System Verilog – UVM (academic, internship, or professional experience)
• A strong understanding of basic Verification concepts, System Verilog design and testbench fundamentals
• Eagerness to learn and apply industry-standard verification methodologies like UVM
• Understanding of debugging workflows and a willingness to learn how to use tools to debug and analyze test issues
• Strong problem‑solving skills, collaborative mindset to work effectively in a team and ability to manage your time effectively
• Fluency in English (mandatory)

Contact

Rita Costa, LinkedIn

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