Senior Principal Chiplet Design Engineer

Cadence is seeking a Sr Principal Design Engineer based in Edinburgh to provide technical leadership for complex Silicon programs. The ideal candidate will have 12+ years of experience in the microelectronics industry and will work closely with the Chiplet Architecture team.

Key responsibilities include leading integration efforts of Cadence IP solutions and participating in technical review meetings. Candidates should possess a degree in Electrical Engineering or a related discipline and strong communication skills.

#J-18808-Ljbffr…