Lead Verification Engineer – SV/UVM Strategy

Chiplogictech is expanding its verification team in Maidenhead, UK. We seek candidates with 5-10 years of experience eager to work on various projects that enhance their technical and verification skills.

The ideal candidate will understand methodologies like SystemVerilog and UVM, be able to define verification strategies, and take on a leadership role as a verification lead. Familiarity with Mentor Questa and Cadence Incisive tools is desirable.

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