Principal Analog Layout Engineer

Principal Analog Layout Engineer- Minimum 5 years experience but ideally >8+ years Experience- experience in 65nm and below(ideally 22nm and below)- understanding of layout for critical timing (PLL, DLL, clock distribution)- understanding of matching techniques for timing circuits and current cells- chip finishing experience a bonus- experience of Cadence PVS/QRC/Pegasus

Senior Analog & AMS Recruitment Specialist

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