Senior SoC RTL Design Engineer Hybrid Role

Arm in Cambridge seeks a dedicated engineer to join their Front End design team, focusing on the specification, design, and verification of complex SoC solutions.

The ideal candidate should have hands-on experience with SystemVerilog or Verilog HDL and a solid understanding of RTL design. A hybrid working environment and a competitive salary range of £73,500 – £99,500 per year are offered.

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