RISC-V Interconnect Architect: Configurable RTL Generators

A leading technology company in Cambridge is seeking a passionate staff level hardware engineer to design industry-leading CPU and interconnect IP. Responsibilities include architecting enhanced TileLink interconnects and implementing RTL generators. Candidates should have a strong software engineering background and proficiency in Verilog, SystemVerilog, or VHDL. This opportunity offers a competitive salary range of $158,760.00 – $194,040.00, comprehensive benefits, and a commitment to an inclusive work environment.#J-18808-Ljbffr…