Physical Design Engineer II — Tapeouts, HP/LP at 7nm

SVENTL ASIA PACIFIC PTE. LTD. in the United Kingdom seeks an experienced ASIC backend engineer to deliver the full netlist-to-GDSII flow, manage tapeouts, and optimize block-level floor planning and power distribution.

You will work on HP cores across 7nm/10nm/14nm/28nm nodes, perform timing signoff in STA/ECO cycles, and use TCL scripting to drive tool flows. Proficiency with ICC/ICC2 and Cadence Innovus is required.

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