Job Overview
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next‑generation, high‑performance, power‑efficient GPU. You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. This exciting role requires a mix of strategic engineering along with hands‑on, technical work.
Key Responsibilities
- Realize the complete electrical analysis closure from early design planning to tape‑out.
- Design power grid specifications that achieve the best balance between power integrity targets and PNR performance, power and area (PPA).
- Define on‑die power switch topology, wake‑up schemes, and in‑rush control.
- Collaborate with internal teams to drive bump map, custom RDL routing, and package design/optimization.
- Develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges.
- Perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions.
- Communicate and drive the needs of PD and Electrical Analysis with cross‑functional teams to enable achieving the goals of the back‑end design for the project.
Qualifications
- Experience planning, implementing, and analyzing power delivery networks.
- Experience designing and analyzing power delivery schemes with power switches.
- Experience with signal/power integrity checks including electromigration, static IR, and dynamic voltage drop checks.
- Experience with global power integrity tools (e.g., Redhawk, Voltus).
- Minimum of BS/MS in EE plus several years of relevant experience.
- Experience with on‑die high‑frequency power delivery and exposure to off‑die concepts and models.
- Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios.
- Familiarity with ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
- Background with large SoC designs (over 20M gates) with frequencies in excess of 1GHz using innovative technologies.
- Track record in solving complex PD and cross‑functional problems, driving results directly and/or directing a team of engineers to innovate and execute on world‑class GPU designs.
- Circuit design and simulation background is a plus, but not required.
- Experience with global timing verification, SPICE simulation/analysis, and Physical Design Verification flows.
EEO Statement
At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more. At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here – in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
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