Job Title
Sr Principal Design Engineer
Location
Edinburgh, United Kingdom
Reports To
Design Engineering Group Director
Job Overview
The Cadence Silicon Solutions Group (SSG) develops leading edge Intellectual Property (IP) and Chiplet Solutions for a variety of high-tech markets. The Cadence IP & Chiplet solutions allow our customers to tackle silicon product development in a system context, enabling them to focus on product differentiation and reduce time to volume. The Cadence vision is to deliver industry‑leading IP & Chiplet solutions to enable our customers to be successful across fast‑moving application spaces such as Physical AI, data centre, and high performance computing. The Sr Principal Design Engineer will be based in Edinburgh as part of an experienced front‑end engineering team, working with our global chiplet team in Europe, India, and the USA.
Job Responsibilities
- Technical leadership of complex silicon programs consisting of leading‑edge IP
- Work closely with the Chiplet Architecture team to define next‑generation Chiplets
- Integration of Cadence IP solutions (e.g., UCIe, PCIe, Ethernet, USB, NPU, Audio, Vision)
- Integration of partner IP solutions (e.g., CPUs, ISP, silicon monitors, NoCs)
- Hands‑on leadership of RTL, testbench, formal analysis and trial synthesis activities
- Quality assurance via implementation of hierarchical lint, cdc and release flows
- Planning of activities and milestones for Chiplet subsystems and system IP development
- Leadership of cross‑functional technical meetings with domain leads (e.g., verification, SW)
- Support customer pre‑sales and post‑sales meetings
- Participate in technical review meetings and checklist reviews as part of ISO‑9001
- Represent Cadence by presenting at industry conferences such as IEEE, DAC, CDNLive
Job Qualifications
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 12+ years’ experience in the microelectronics/EDA industry
- Experience with Verilog RTL design
- Experience with metric‑driven verification (MDV)
- Experience with front‑end design tools covering lint, synthesis, cdc analysis
- Experience with SoC architecture and development
- Experience with technical team leadership
- Excellent oral and written English
- Self‑motivated with excellent planning, interpersonal, and communication skills
Preferred Skills
- Experience with AMBA, PCIe, CXL & UCIe protocols
- Experience with quality processes such as ISO‑9001 & ISO‑26262
Travel
10%
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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