Senior Principal Design Engineer: Chiplet IP & RTL Leader

Cadence Edinburgh is seeking a Sr Principal Design Engineer to lead complex silicon programs and drive frontend design activities within a seasoned team. You will collaborate with Chiplet Architecture to define next‑generation Chiplets and oversee the integration of Cadence IP and partner IP across PCIe, UCIe, and related interfaces.

You will lead RTL, testbench, formal analysis and verification efforts, ensuring high‑quality deliverables and adherence to ISO‑9001 processes, while engaging with

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